Optimal Tuning of AGDs Parameters and a Technique for Testing the Correct Mounting of Heatsinks on Power Transistors

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A SPICE model of Operational Amplifiers for Electromagnetic Compatibility Analysis

This article proposes a macromodel to predict the nonlinear behavior of operational amplifiers having their baseband signal affected by out-of-band disturbances, such as those caused by electromagnetic interference. Like any opamp macromodel, the one proposed in this work was developed with the purpose of not sharing neither the technology parameters nor the circuit topology of the real device. Besides the baseband macromodel, the proposed solution comprises a high frequency equivalent circuit that propagates the out-of-band signals, and a nonlinear model to account for their demodulation. The proposed solution is suitable for any SPICE-like simulator. It does not affect the simulation performance, meaning the simulation time, the simulation accuracy and it does not cause any convergence issue. This article shows in detail the macromodel, the method to calculate its parameters as well as its experimental validation, which was obtained comparing the model predictions with the results of the measurements carried out on a commercial device

Test Solution for Heatsinks in Power Electronics Applications

Power electronics technology is widely used in several areas, such as in the railways, automotive, electric vehicles, and renewable energy sectors. Some of these applications are safety critical, e.g., in the automotive domain. The heat produced by power devices must be eciently dissipated to allow them to work within their operational thermal limits. Moreover, numerous ageing eects are due to thermal stress, which causes mechanical issues. Therefore, the reliability of a circuit depends on its dissipation system, even if it consists of a simple passive heatsink mounted on the power device. During the Printed Circuit Board (PCB) production, an incorrect assembly of the heatsink can cause a worse heat dissipation with a significant increase of the junction temperatures (Tj). In this paper, three possible test strategies are compared for testing the correct assembling of heatsinks. The considered strategies are used at the PCB end-manufacturing. The eectiveness of the dierent test methods considered is assessed on a case study corresponding to a Power Supply Unit (PSU)

A New Approach to Characterize Complex ICs in Terms of Scattering Parameters

The macro-models used in chip-level EMC analysis usually comprise equivalent circuits whose parameters are derived from the results of scattering parameter measurements. The constant increment of IC complexity along with the increment of the pin number has made this job difficult to accomplish, because of the numerous measurements to carry out and the propagation of related errors. Aiming to address this issue, this paper explores the possibility to obtain the scattering parameter matrix of an N-port system from measurements carried out with an m-port vector network analyzer, with the remaining N-m ports left open or loaded with a set of known impedances. According to the definition of scattering parameters, the measurement must be carried out with the ports loaded by their respective characteristic impedance (usually 50Ω ), which makes such measurements time-consuming, especially with devices featuring many ports. This is mostly because the N-m port not connected to the VNA must be matched during the measurement process. This paper presents a method that allows one to obtain the scattering matrix of an N-port device, using the S-par measurements carried out with the N-m ports not connected to the VNA, left open. The proposed technique requires ( ) set of measurements (Fig. 1), but there is no need to match with the reference impedances the port of DUT that are not connected to the VNA during the measurement process. To this purpose, three different methods suitable to derive the scattering parameters with the remaining N-m ports mismatched are available in literature. All these algorithms are based on two-step matrix transformation: the first step, starting from mismatched measured parameters, builds a set of partial matrices (S^p) containing the information related to the auxiliary load, while the second one reconstructs the true S parameter matrix from the partial matrices obtained in the first step. The great advantage of this approach is that the port not connected to the VNA can be left open. Unfortunately, this condition could be problematic because the parasitic elements loading the port not connected to the VNA, could affect the elements of the extracted matrix, especially at high frequency. The use of these techniques significantly reduces the number of steps needed to extract the final matrix. Aiming to check the proposed method, a three port IC was characterized using a 2-port VNA. At first, the scattering parameters resulting from the proposed procedure and those obtained using the definition of scattering parameters do not match in some frequency ranges. The mathematical analysis carried out afterwards pointed out that the observed errors deal with the conditioning number of the matrix to be inverted in the second step. Furthermore, the more the reflection coefficient magnitude of the auxiliary loads is close to one, the higher is the probability to obtain a high condition number, increasing the error of the reconstructed matrix. Therefore, in order to avoid the matrix inversion in ill conditioned point, the Newton's method was chosen as the optimal solution and its goodness was checked by repeating such a test on the above-mentioned circuit, as shown in Fig. 2

A New Approach to Characterize Complex ICs in Terms of Scattering Parameters

The macro-models used in chip-level EMC analysis usually comprise equivalent circuits whose parameters are derived from the results of scattering parameter measurements. The constant increment of IC complexity along with the increment of the pin number has made this job difficult to accomplish, because of the numerous measurements to carry out and the propagation of related errors. Aiming to address this issue, this paper explores the possibility to obtain the scattering parameter matrix of an N-port system from measurements carried out with an m-port vector network analyzer, with the remaining N-m ports left open or loaded with a set of known impedances. According to the definition of scattering parameters, the measurement must be carried out with the ports loaded by their respective characteristic impedance (usually 50Ω ), which makes such measurements time-consuming, especially with devices featuring many ports. This is mostly because the N-m port not connected to the VNA must be matched during the measurement process. This paper presents a method that allows one to obtain the scattering matrix of an N-port device, using the S-par measurements carried out with the N-m ports not connected to the VNA, left open. The proposed technique requires ( ) set of measurements (Fig. 1), but there is no need to match with the reference impedances the port of DUT that are not connected to the VNA during the measurement process. To this purpose, three different methods suitable to derive the scattering parameters with the remaining N-m ports mismatched are available in literature. All these algorithms are based on two-step matrix transformation: the first step, starting from mismatched measured parameters, builds a set of partial matrices (S^p) containing the information related to the auxiliary load, while the second one reconstructs the true S parameter matrix from the partial matrices obtained in the first step. The great advantage of this approach is that the port not connected to the VNA can be left open. Unfortunately, this condition could be problematic because the parasitic elements loading the port not connected to the VNA, could affect the elements of the extracted matrix, especially at high frequency. The use of these techniques significantly reduces the number of steps needed to extract the final matrix. Aiming to check the proposed method, a three port IC was characterized using a 2-port VNA. At first, the scattering parameters resulting from the proposed procedure and those obtained using the definition of scattering parameters do not match in some frequency ranges. The mathematical analysis carried out afterwards pointed out that the observed errors deal with the conditioning number of the matrix to be inverted in the second step. Furthermore, the more the reflection coefficient magnitude of the auxiliary loads is close to one, the higher is the probability to obtain a high condition number, increasing the error of the reconstructed matrix. Therefore, in order to avoid the matrix inversion in ill conditioned point, the Newton’s method was chosen as the optimal solution and its goodness was checked by repeating such a test on the above-mentioned circuit, as shown in Fig. 2

A Criterion for an Optimal Switching of Power Transistors

Power converters, especially those exploiting fast-switching devices, suffer from ringing, which worsens efficiency, EMI performance and increases the stress of components. Traditional approaches, such as RC snubber and series gate resistance, only partially mitigate the problem, whereas, active gate driver implies sub-optimal switching waveforms. This paper presents a new criterion for controlling the turn-on and the turn-off of a power transistor using a three-levels current driver, which results in optimal switching waveforms. The method shows better performance in terms of efficiency and transient slopes compared to traditional approaches

Novel Solutions to Reduce the EM Emissions of Power Switching Circuits

The introduction of wide bandgap (WBG) devices in power modules has led to increased system efficiency, since those transistor switch faster. This, however, results also in increased electromagnetic emissions. In the last years, the research activity has tried to develop software techniques in order to address such an issue. Among them, the spread spectrum technique can be used, but this approach does not reduce the EM emission energy. In order to reduce the electromagnetic interference (EMI) energy, a first approach, that can be used whenever there are a pair of nodes switching opposite, consist in aligning the transition edges, reducing the common mode emissions significantly. However this approach is not sufficient, since the waveform edges are not perfectly equal and opposite, since the rising and falling time differ and some ringing can be present. To address this issue, recent investigations have shown that the switching transistors can be driven so that they behave as switches and as snubbers, simultaneously

Investigation on the Switching Waveforms of GaN Power Devices to Gate Current Profiles

The extended use of Gallium Nitride (GaN) transistors in power applications, such as automotive, industrial and power distribution, leads practitioners and researchers to a review of the classical driving techniques, to meet the different characteristics of such devices compared to traditional ones, such as MOS and IGBT. In particular, the smaller intrinsic capacitances of GaN transistors allows faster switching transitions, thus decreasing the power dissipation during commutations. On the other hand, the higher slope of the switching waveforms drives high frequency resonant circuit that, using slower devices, would not be excited. This paper proposes a technique to obtain an optimal pair of non-oscillating switching waveforms, which exploits time-varying resistances in the power loop. A gate charge driving technique, based on the modulation of the gate current, is exploited for shaping the optimal waveforms by means of the power transistor itself. A simulation analysis was carried out considering two different driving waveforms and studying the sensitivity of ringing as a function of their significant parameters. Such analysis highlights that the optimal switching waveforms can be obtained by means of several driving shapes. Finally, a comparison with the RC snubbered circuit, in terms of efficiency and ringing, is reported to highlight the advantages of the proposed technique

Testing Heatsink Faults in Power Transistors by means of Thermal Model

In safety-critical systems, power electronics is widely used, e.g., for driving actuators. High currents and high voltages are often used in power electronics, which may cause considerable heating of the power devices. Hence, different mechanisms for heat dissipation and cooling of power devices are adopted. An excessive temperature increase in the power devices may lead to considerable electrical and mechanical stresses, and overheated electrical devices are subject to more rapid ageing. Therefore, an incorrect behaviour of the dissipation system can seriously damage or even block a safety-critical system. Hence, it is necessary to introduce test mechanisms to check the correct behaviour of the heatsinks. In this paper, we propose a strategy to quantitatively evaluate the effectiveness of a test for the dissipation system. The proposed approach is based on an electrothermal model of the cooling system. It allows one to identify the maximum size of the thermal fault tolerated by the dissipation system before the electrical device break down